In the recent development of semiconductor fabrication technologies, the replacement of aluminum-copper alloy by pure copper as a chip interconnection material results in numerous advantages in the chip performance. Conventionally, aluminum-copper and its related alloys have been used as a preferred metal conductor material for forming interconnections on electronic devices such as IC chips. The copper content in an aluminum-copper alloy is limited typically to a range between about 0.3 and about 4%.
The chip performance made possible by pure copper or copper alloys includes a lower electrical resistivity since the resistivity of copper and certain copper alloys is less than the resistivity of aluminum-copper. Based on the low resistivity of copper, narrower lines can be used and higher wiring densities can also be realized.
While the advantages of copper metalization have been recognized by many in the semiconductor industry, copper metalization has been the subject of extensive research effort in recent years. Semiconductor processes such as chemical vapor deposition (CVD) and electroless plating are popularly used for depositing copper. Both of these methods of deposition produce at best conformal deposits and sometimes lead to defects such as voids in a wiring structure, especially when trenches are deposited which have a cross-section narrower at the top than at the bottom as a result of an imperfect reactive ion etching process. Similarly, while the electroless plating technique offers the advantage of low cost, the evolution of hydrogen gas during deposition leads to blistering and other void defects which are detrimental to the quality and reliability of IC devices built.
One such electroplating processes for depositing copper, silver or gold onto a semiconductor wafer is described in U.S. Pat. No. 5,256,274 issued in 1993. In this patent, a copper conductor which is obtained with a seam at is center is judged as a good deposition while a copper conductor with a void at its center is judged as bad deposition. The plating bath utilized in the patent contains 12 ounces/gallon of water of CuSO4·5H2O, 10% by volume of concentrated sulfuric acid, 50 ppm of chloride ion from hydrochloric acid, and TECHNI-COPPER® W additive at 0.4% by volume provided by Technic, Inc. of Providence, R.I. The plating glasses were selectively deposited through an inert mask.
The electroplated copper that is presently being used as line and via level interconnections in semiconductor devices suffers from an initially high resistance which requires either a long time, i.e., three days, room temperature anneal or some shorter time elevated temperature anneal to reduce the films to acceptable resistance levels. Typically, electroplated copper films are deposited in a fine grained condition from baths that contain additives or dopants. With time, these initially small copper grains, i.e., in the range of approximately 20 nm, grow to a final large grain, i.e., in the range of 1,000 nm low stress microstructure during which time a resistance drop of approximately 20˜30% occurs. The large grained, low resistance, plated copper is preferred since it has both better electromigration stress voiding behavior than fine grained copper films and the desired high electrical conductivity.
The plated copper films that are presently used in semiconductor devices as line and via level interconnections suffer from an initially high resistance which requires either a long time period, i.e., three days room temperature anneal or shorter time at elevated temperatures, to reduce the high resistance to acceptable resistance levels. The long anneal times required therefore places unacceptable limits on the fabrication process which results in a more expensive copper process. In order to speed up the fabrication processes, it is important that this grain growth and associated resistance drop, i.e., the resistance transient, occur in as short a time as possible.
It is therefore an object of the present invention to provide a method for plating copper conductors on an electronic substrate that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for plating copper conductors on an electronic substrate which produces copper films with short resistance transient.
It is a further object of the present invention to provide a method for plating copper conductors on an electronic substrate by carrying out the electroplating process in a plating bath maintained at a temperature below 18° C.
It is another further object of the present invention to provide a method for plating copper conductors on an electronic substrate wherein copper films of large grain size and low electrical resistance are plated.
It is still another object of the present invention to provide a method for plating copper conductors on an electronic substrate wherein copper films of low resistance transient are plated in a bath maintained at a low temperature and a low additive concentration of not more than 5 mL/L.
It is yet another object of the present invention to provide a method for plating copper conductors on an electronic substrate for producing copper films of short resistance transient wherein a low electrical resistance plated film can be obtained in less than 10 hours of room temperature annealing.
It is still another further object of the present invention to provide a method for plating copper conductors in a structure of high aspect ratio by a two-step plating process wherein two copper layers are separately plated.
It is yet another further object of the present invention to provide a method for plating copper conductors in a high aspect ratio via opening by plating a first layer of copper in a plating bath containing high additive concentration and then plating a second layer of copper in a plating bath containing low additive concentration such that a copper film of short resistance transient is obtained.